The present invention relates to a non-volatile semiconductor memory device having electrically erasable, writable and readable functions. More particularly, the present invention relates to a non-volatile semiconductor memory device capable of executing these functions at the same time.
In electrically batch-erasable, writable, and readable non-volatile semiconductor memory devices, erase and write operations require several hundred- to several hundred thousand-folds operation time relative to a read operation. Therefore, a single non-volatile semiconductor memory device can carry out neither a write operation nor a read operation during an erase operation and, can carry out neither an erase operation nor a read operation during a write operation.
Accordingly, in order to carry out erase, write and read operations simultaneously, a system such as electrical products need to have multiple non-volatile semiconductor memory devices so that while an erase or write operation is carried out with one non-volatile semiconductor memory device, a read operation with another non-volatile semiconductor memory device.
JP-A 7/281952 discloses a method of carrying out simultaneously two or more functions of erase, write, and read operations. A method using a latch circuit is described in FIG. 7 as a Conventional Example 1, and a method using a selector circuit in FIG. 8 as a Conventional Example 2. The prior art disclosed in JP-A 7/281952 will be illustrated hereinafter by referring to FIGS. 7 and 8.
FIG. 7 shows a block diagram representing a constitution of the Conventional Example 1. A non-volatile semiconductor memory device (IC) 1 comprises a control signal 2 entered from outside, data 3, address 4, and a power supply 5. A command analyzing and status data generating part 6 analyzes a command entered as data 3, and controls the whole of IC 1.
The IC 1 further comprises an erase control part 7 and a write control part 8. The erase control part 7 transmits a status signal 7a to communicate that the erase control part 7 is busy to the command analyzing and status data generating part 6, a request signal 7b which is transmitted to the command analyzing and status data generating part 6 before the erase control part 7 uses a bus 9 (9axcx9c9h, 9i), and an acknowledge signal 7c to communicate that the bus 9 (9axcx9c9h, 9i) is able to be used to the erase control part 7 when the command analyzing and status data generating part 6 obtains the request signal 7b. The write control part 8 transmits a status signal 8a to communicate that the write control part 8 is busy to the command analyzing and status data generating part 6, a request signal 8b which is transmitted to the command analyzing and status data generating part 6 before the write control part 8 uses a bus 9 (9axcx9c9h, 9j), and an acknowledge signal 8c to communicate that the bus 9 (9axcx9c9h, 9j) is able to be used to the erase control part 7 when the command analyzing and status data generating part 6 obtains the request signal 8b. 
The bus 9 (9axcx9c9h) transmits an address signal, a data signal, and a control signal from the command analyzing and status data generating part 6, the bus 9i connects the bus 9 to the erase control part 7, and the bus 9j connects the bus 9 to the write control part 8. Memory blocks 10axcx9c10h are composed of a row decoder, a column decoder, a sense amplifier and a memory array cell. Latch circuits 11axcx9c11h temporarily memorize each of an address signal, a data signal and a control signal from the buses 9axcx9c9h and transmit these signals to the memory blocks 10axcx9c10h. The data once latched are never altered except when they are altered by controlling by the command analyzing and status data generating part 6. Buses 12axcx9c12h connect the latch circuits 11axcx9c11h. 
In FIG. 8, buses 14 (14axcx9c14h) are for erasing, and transmit each of an address signal, a data signal and a control signal from the erase control part 7 to the memory blocks 10axcx9c10h, and buses 15 (15axcx9c15h) are for writing, and transmit each of an address signal, data signal and control signal from the write control part 8 to the memory blocks 10axcx9c10h. Selector circuits 13axcx9c13h select one of signals from bus 14 for erasing, bus 15 for writing and bus 9, to transmit the selected signal to the memory blocks 10axcx9c10h. 
Next, operations will be explained below.
First, a read operation is explained.
When a read signal consisting of a control signal 2 and an address 4 is entered into the command analyzing and status data generating part 6 from the outside, the command analyzing and status data generating part 6 confirms whether a memory block from which data are to be read is busy on an erase operation or a write operation. If the memory block from which data are to be read is busy, then, a status of error is returned to the outside via the data 3. If the memory block from which data are to be read is not busy, then, a read signal is transmitted through the bus 9, the latch circuit 11, and the bus 12 to the memory block 10 to read data from a memory cell in the memory block.
Subsequently, the data to be read are sent from the memory block 10 through the bus 12, the latch circuit 11, and the bus 9 to the command analyzing and status data generating part 6 and, then, the read operation is completed when the data which have been read are sent to the outside through the data 3. Additionally, whether the memory block is busy or not is confirmed by transmitting a read signal to the latch circuits 11axcx9c11h, and by thereupon returning a busy signal indicating on operation from the latch circuit 11 to the command analyzing and status data generating part 6.
Second, a write operation is explained.
When a write signal consisting of the control signal 2 and an address signal 4, and data to be written and entered through data 3 are entered into the command analyzing and status data generating part 6 from the outside, the command analyzing and status data generating part 6 transmits an operation starting signal to the write control part 8 through the bus 9j after having confirmed that the memory block to which data is to be written is not in erasing (on operating) (i.e., after having confirmed that a busy signal indicating on an operation is not returned from the latch circuit 11, but a read signal indicating on-waiting for a subsequent operation is returned). Then, the write control part 8 makes a status signal 8b indicating on a write operation active.
The write control part 8 sends a request for using the bus 9 by a request signal 8b to the command analyzing and status data generating part 6, and when it receives the permission for use of the bus 9 as an acknowledge signal 8c, it transmits a write signal and data to be written through the bus 9, the latch circuit 11 and the bus 12 to the memory block 10, at this point in time, a write operation starts.
In order to write data, it is needed to keep applying a voltage required to write data to the memory cell for a certain period of time and, this voltage is also applied via the common bus 9. Therefore, arbitration of using the bus 9 is required. Specifically, since a write operation spends a relatively long time, a read operation is restricted when the write operation is carried out. Consequently, the effect of simultaneous operation is reduced. Therefore, time sharing of the write operation is performed to permit a read operation between the periods of the write operation.
In order to interrupt the write operation once, the state of the bus 9 is saved in the latch circuit 11 and, the operation state of the memory block to which data is written is maintained. After that, the request signal is made to be non-active to open the bus 9 to the command analyzing part and status data generating part 6. In order to resume the write operation after a certain period has elapsed, the request signal 8b is made to be active so that the write control part 8 can send again a request for using the bus 9, and thereafter it waits the return of the acknowledge signal 8c from the command analyzing and status data generating part 6. The period during which the write control part 8 releases the bus 9 is controlled using an inner timer. When the write operation has completed by repeating these operations, the write operation is quitted and, then, in a similar way, the use of the bus 9 is requested to enter a write verifying operation. If the verification result is normal (OK), then, the completion of the write operation is sent to the command analyzing and status data generating part 6 via the status signal 8a, and the write control part 8 quits the operation, the write operation is completed. If the verification result is abnormal (NG), then, the memory cell is made to be in the write status again to carry out the write verifying. These operations are repeated a predetermined times to return a status of write error from the command analyzing and status data generating part 6 to the outside via data 3.
Third, an erase operation is explained.
Basically, a procedure of the erase operation is the same as that of the write operation, except for the voltage applied to the memory cell and the applying time thereof (in the current mass production, the time for an erase operation is longer than that for a write operation by three places). That is, when an erase signal consisting of a control signal 2, a data 3 and an address 4, and erase data are sent to the command analyzing and status data generating part 6 from the outside, after the command analyzing and status data generating part 6 confirms that the memory block in which data are to be erased is not in writing (on operation), it transmits an operation starting signal to the erase control part 7 via the bus 9i. Then, the erase control part 7 makes a status signal 7a indicating on an erase operation active. The erase control part 7 sends a request for using the bus 9 by a request signal 7b to the command analyzing and status data generating part 6, and when it receives the permission for use of the bus 9 as an acknowledge signal 7c, it transmits an erase signal through the bus 9, the latch circuit 11, and the bus 12 to the memory block 10, at this point in time, an erase operation starts. In order to erase data, since it is needed to keep applying a voltage required to erase data to the memory cell for a certain period of time, the function of the latch circuit 11 makes the memory block 10 to be in a holding state, temporarily stops the use of the bus 9, and makes the request signal 7b non-active to communicate the evacuation of the bus 9 to the command analyzing and status data generating part 6.
After a certain period of time as measured with an inner timer, the erase control part 7 makes again the request signal 7b active and, then, the erase control part 7 waits the return of the acknowledge signal 7b from the command analyzing and status data generating part 6. When the permission for the use of the bus 9 returns as the acknowledge signal 7c, the erase control part 7 occupies the bus 9, in order to make the memory cell carry out an erase verifying operation, it transmits a signal through the bus 9, the latch circuit 11 and the bus 12 to the memory block 10, and stops the erase operation to enter the erase verifying operation. If the verifying result is normal (OK), then, the completion of the erase operation is sent to the command analyzing and status data generating part 6 via the status signal 7a, and the erase control part 7 quits the operation, the erase operation is completed. If the verify result is abnormal (NG), then, the memory cell is made to be in the erase state again to carry out the erase verifying. These operations are repeated a predetermined times to return a status of write error from the command analyzing and status data generating part 6 to the outside via data 3.
The erase, write and read operations are carried out in this way and, thus, for example, while the erase operation is carried out in the memory block 10a and the write operation is carried out in the memory block 10b, the read operation can be carried out in the memory block 10c. Naturally, when the read operation is carried out continuously, since interruptions of the request signal 7b and the acknowledge signal 7c sometimes occur between the read operations, the access time is partially extended. In general, this merely means that waits occur during the memory access, a busy time is long, or the return of the acknowledge signal delays. Therefore, the system can be used without problems in operations.
FIG. 8 shows a block diagram presenting the constitution of the Conventional Example 2.
First, a read operation is explained.
When a write signal consisting of a control signal 2 and an address 4 is entered into the command analyzing and status data generating part 6 from the outside, the part 6 confirms whether a memory block from which data is to be read is on an erase operation or a write operation. If the memory block from which data are to be read is busy, then, a status of error is returned to the outside via data 3. If the memory block from which data are to be read is not busy, then, a read signal is transmitted through a bus 9, a selector circuit 13 and a bus 12 to the memory block 10 to read data from a memory cell in the memory block. Subsequently, the data to be read are sent from the memory block 10 through the bus 12, the selector circuit 13 and the bus 9 to the command analyzing and status data generating part 6 and, then, the read operation is completed when the data to be read are sent to the outside through the data 3.
Additionally, whether a memory block is busy or not is confirmed by transmitting a read signal to the selector circuit 13, and by thereupon returning a busy signal indicating on the erase or write operation from the selector circuit 13 to the command analyzing and status data generating part 6 when the selector circuit 13 selects the bus 14 or the bus 15.
Second, a write operation is explained.
When a write signal consisting of the control signal 2 and an address 4, and data to be written and entered through data 3 are entered into the command analyzing and status data generating part 6 from the outside, the command analyzing and status data generating part 6 transmits an operation start signal to the write control part 8 through the bus 9j after having confirmed that the memory block to which data is to be written is not in erasing (on operating) (i.e., after having confirmed that a busy signal indicating on operation is not returned from the selector circuit 13, but a read signal indicating on waiting for a subsequent operation is returned).
Then, the write control part 8 makes a status signal indicating on a write operation active. The write control part 8 transmits a write signal and a write data through the selector circuit 13 and the bus 12 to the memory block 10 via the bus 15 for a write operation and, then, the write operation starts. After applying a voltage required to write to the memory cell for a certain period of time, verifying is carried out. If the verify result is normal (OK), then, the write operation is completed, the write control 8 makes the status signal 8b non-active, and sends the completion of the write operation to the command analyzing and status data generating part 6. If the verify result is abnormal (NG), then, it reenters the write and verifying operations. These operations are repeated predetermined times, when the verifying result is abnormal (NG), a status of write error is sent from the command analyzing and status data generating part 6 to the outside via data 3. Additionally, when a voltage is applied to the memory cell for a certain period of time, the applying time is controlled using an inner timer in the write control part 8.
This conventional Example 2 is characterized in that, for example, since it has a bus 15 for writing and, consequently, it is not needed to arbitrate the use of a single bus 9 by using the request signal 8b and the acknowledge signal 8c, the write control 8 controls the whole process from the start to the completion for writing during the write operation, so that the selector circuit 13 and the memory block 10 can be occupied. Thus, since the write operation is not affected by other than the circuits of the write control part 8, the selector circuit 13 and the memory block 10, the operation speed is high.
Third, an erase operation is explained.
Basically, a procedure of the erase operation is the same as that of the write operation. That is, when an erase signal consisting of a control signal 2, data 3 and an address 4, and an erase data are sent to the command analyzing and status data generating part 6 from the outside, after the command analyzing and status data generating part 6 confirms that the memory block in which data are erased is not in writing (on operation) (i.e., after having confirmed that a busy signal indicating on operation is not returned from the selector circuit 13, but a read signal indicating on waiting for a subsequent operation is returned), it transmits an operation starting signal to the erase control part 7 via the bus 9i. 
Then, the erase control part 7 makes a status signal 7a indicating on an erase operation active. The erase control part 7 transmits a signal to the selector circuit 13, the bus 12 and the memory block 10 via the bus 14 for erasing, at this point in time, an erase operation starts. After applying a voltage required to erase to the memory cell for a certain period of time, verifying is carried out. If the verify result is normal (OK), then, the erase operation is completed, and the erase control 7 makes the status signal 7b non-active, and sends the completion of the erase operation to the command analyzing and status data generating part 6.
If the verify result is abnormal (NG), then, it reenters the write and verifying operations. These operations are repeated predetermined times, when the verify result is abnormal (NG), a status of write error is sent from the command analyzing and status data generating part 6 to the outside via data 3.
Since the control of the erase, write and read operations are, in this way, carried out, respectively, via independent buses 14, 15 and 9 and, then, for example, while the erase operation is carried out in the write control part 8, the buses 15 and 15a for writing, the selector circuit 13a, the bus 12a and the memory block 10a, and the erase operation is carried out in the erase control part 7, the buses 14 and 14b for erasing, the selector circuit 13b, the bus 12b and the memory block 10b, the read operation can be carried out in the command analyzing and status data generating part 6, the buses 9 and 9c, the selector circuit 13c, the bus 12c and the memory block 10c. 
The market of an electrically-rewritable non-volatile semiconductor memory device represented by, for example, a flash memory increases mainly in the field of portable phones and, further, multi-functionalization and high-functionalization rapidly progress. Therefore, the specifications demanded for the non-volatile semiconductor memory devices are being diversified, it becomes difficult to meet the demand in the market with a fixed specification determined at the stage of the circuit designing as conventional.
However, in the non-volatile semiconductor memory devices described above, a selector circuit and a latch circuit correspond to memory blocks one to one, a single selector circuit controls a single memory block so that the memory region controlled by the single selector circuit is fixed at the stage of the circuit designing and, then, it can not be altered. That is, in the single non-volatile semiconductor memory device, a size of the memory region is fixed where two or more functions from erasing, writing and reading can be carried out at the same time, and the size is never altered except when the device is re-designed.
Thus, the present invention has been made to flexibly satisfy the diversifying market demand, and an object of the present invention is to provide a non-volatile semiconductor memory device which can alter the memory size according to the demanded specification where two or more functions can be carried out at the same time, and which can further alter the memory size dynamically.
In order to solve the above problem, the present inventors have introduced a novel concept, termed xe2x80x9cpartitionxe2x80x9d, and have developed a non-volatile semiconductor memory device which can carry out erasing, writing and reading at the same time by a partition unit.
The partition according to the present invention includes a plurality of memory blocks, wherein the number of the memory blocks contained in one partition may be altered with a command control from the outside.
The non-volatile semiconductor memory device of the present invention has a plurality of erasable, writable and readable memory segments, and can carry out erase, write and read functions simultaneously by altering a combination of these memory segments. Thus, distribution of memory segments to be used can be effectively performed according to the purpose of using by altering the memory segments where these functions can be carried out at the same time. That is, the present invention provides a non-volatile semiconductor memory device which can flexibly satisfy the diversifying market demand. In addition, since the alteration of the memory region distribution is possible by entering a command, the distribution of memory segments to be used can be effectively preformed anytime according to the purpose of use.
A non-volatile semiconductor memory device of the present invention (claim 1) has a memory region comprised of a plurality of memory segments which are electrically batch-erasable, writable, and readable, each of the plurality of memory segments being independently operable from each other, said non-volatile semiconductor memory device comprising a memory-region-division-information holding-mean which holds a memory region division information for dividing the memory region into a plurality of memory segment groups comprising at least one memory segment, and a memory-segment-group selecting-mean which generates a signal for selecting a memory segment group to all the memory segments belonging to the each of the memory segment groups according to the held memory-region-division-information holding-mean.
That is, a constitution of a memory segment group comprising one or more memory groups (hereinafter, referred to as xe2x80x9cpartitionxe2x80x9d) is determined by memory region division information which is held by a memory-region-division-information holding-mean, and selection of memory segments constituting one partition is carried out by a memory-segment-group selecting-mean.
The non-volatile semiconductor memory device of the present invention (claim 2) is characterized in that the memory region division information held in the memory-region-division-information holding-mean is fed by entering a command from the outside.
That is, the constitution of the partition can be altered by entering a command.
The non-volatile semiconductor memory device of the present invention (claim 3) is characterized in that the memory segment group for which the memory-segment-group selecting-mean generates a selecting signal is directed by entering an address from the outside.
That is, a partition to be accessed is selected arbitrarily by entering an address from the outside.
The non-volatile semiconductor memory device of the present invention (claim 4) is characterized in that the memory segment comprises a memory block, a latch circuit holding an operation state of the memory block, and a selector circuit selecting any of signals required to erase, write and read, and transmitting the selected signal to the memory block.
The non-volatile semiconductor memory device of the present invention (claim 5) is characterized in that the selector circuit selecting any of the signals required to erase, write and read is controlled by the selecting signal from the memory-segment-group selecting-mean or an operation state of the memory block which is held in the latch circuit.
That is, the memory segment constituting a partition comprises a memory block, a latch circuit and a selector circuit. When an operation is carried out to the partition, since a signal corresponding to the operation is selected and, subsequently, the status of the operation is memorized, during the operation of in this partition, another operation can be carried our in another partition.
The non-volatile semiconductor memory device of the present invention (claim 6) is characterized in that a circuit holding information in the memory-region-division-information holding-mean comprises a non-volatile memory.
That is, once the constitution of the partition has been set up, the information is held after the power is shut down.
The non-volatile semiconductor memory device of the present invention (claim 7) is characterized in that a circuit holding information in the memory-region-division-information holding-mean comprises a volatile memory.
That is, by using a volatile memory, a write speed is enhanced, and a temporary, dynamic alteration of the partition constitution can be carried out even while the circuit is used.
The non-volatile semiconductor memory device of the present invention (claim 8) is characterized in that a circuit holding information in the memory-region-division-information holding-mean comprises both a non-volatile memory and a volatile memory.
That is, after the power is turned on, a partition constitution can be temporarily and dynamically altered from the preset initial state.
The non-volatile semiconductor memory device of the present invention (claim 9) is characterized in that the memory-region-division-information holding-mean has a protection-information holding-mean which holds information for protecting the memory region division information and, further, a mean for prohibiting alteration of the memory region division information according to the held protection information.
That is, it is possible to prevent the partition constitution from being undesirably altered with entry of an incorrect command by setting the protection information.
The non-volatile semiconductor memory device of the present invention (claim 10) is characterized in that information for protecting the memory region division information is given to the protection-information holding-mean by entering a command from the outside.
That is, since the protection information itself is set by entering a command, it is possible to set or cancel the protection as needed.
The non-volatile semiconductor memory device of the present invention (claim 11) is characterized in that it further comprises a mean for invalidating the command entry into the protection-information holding-mean.
That is, it is possible to disapprove in future the alteration of the partition constitution once set by prohibiting setting of the protection information.